SPIE Handbook of Microlithography, Micromachining and Microfabrication
Volume 1: Microlithography
Section 2.6 Data Preparation
2.6 Data Preparation
Preparation of pattern data for electron beam lithography may begin with a high level symbolic or mathematical description of a circuit, with the algorithmic description of a pattern (e.g. a Fresnel lens), or with a simple geometric layout. A computer aided design (CAD) program is usually used to lay out or at least inspect the pattern and to generate output in a standard exchange format. A separate program is then used to convert the intermediate format to machine-specific form. This last step can be quite involved since in most cases all hierarchy must by removed ("flattened"), polygons must be reduced to primitive shapes (e.g., trapezoids or triangles and rectangles), and the pattern must be fractured into fields, subfields, and even sub-subfields.
For shaped beam machines, or if the data is to be proximity corrected, medium and large sized shapes should be "sleeved", so that the edges of shapes are exposed separately from the interiors. For shaped beam machines this allows the edges to be exposed with a small shaped size that has better resolution; for proximity corrected patterns, this allows finer control over the dose delivered to the shapes. Frequently, a bias (also known as sizing) may be applied to the pattern shapes to account for resist characteristics or process steps that affect the final device linewidth.
For Gaussian beam machines, a reasonable pixel size must be selected. A good compromise is usually to use a pixel size of about half the beam diameter. Larger pixel sizes may speed up throughput, while smaller pixel sizes will reduce line edge roughness and improve feature size control. The machine field size is usually a fixed multiple of the pixel size. Field sizes may range from less than 100 um for high resolution, high accuracy work to more than 1 mm for high speed, low resolution lithography.
When designing a device such as a transistor, you would organize the fabrication in a set of steps; e.g., mesa, ohmics, gate, etc. Each step is assigned to a "layer" in the CAD tool, and multiple layers are displayed as overlapping patterns (usually in different colors). Much later on, the layers will be split apart into separate pattern files. Some of these layers may be patterned with photolithography, some with e-beam. For example, you may design the geometry of each layer and place all of this information in the transistor "cell". Now you can put this cell at a number of other locations to create, say, a NAND logic gate. If you have not simply copied the transistor but rather have created instances of the cell (somewhat like a function called in a program) then any modifications in the transistor cell will be instantiated all over the NAND gate. The NAND gate is now a higher level cell, which can be used as part of, say, a half-adder. The hierarchy of an entire circuit is continued in this way. Of course, when building circuits from a standard technology such as CMOS, all of the basic component cells are usually purchased as part of the CAD program (a library of cells), and may even be placed and connected automatically as part of a symbolic CAD package.
An e-beam lithographer would be unlikely to use any high level design tools. Rather, the lithographer must deal with data at the lower, geometrical level. If the scale of critical dimensions is far larger than the e-beam tool's placement errors, then the designer is free to place features anywhere. For instance, a set of 5 reticles with 5 um design rules and 0.5 um overlay error budget will demand little (except stability) of a commercial e-beam system. However, when the design requires a direct-write e-beam layer with 0.05 um alignment, the placement of alignment marks becomes critical, and e-beam stitching errors can significantly affect device performance and yield. It is important for the designer to consider the limitations of the e-beam system before laying out any pattern.
Consider the case of a pattern targeted for a high resolution Gaussian beam system, such as the Leica EBPG or the JEOL-JBX series. For high resolution work the writing field may be as small as 80 um. Larger patterns are formed by moving the sample and stitching fields together. Field stitching errors will be around 20 nm, so any fine lines in the pattern (e.g., a narrow gate) should not be placed at a field boundary.
Electron-beam lithography may be used to pattern optical masks and their corresponding alignment marks; steppers and contact aligners have specific design requirements for these marks. However, we will discuss here only the marks used for direct-write e-beam layers. There are two phases of alignment: (1) correction for the placement and rotation of the wafer (or piece) and (2) correction for the placement of individual chips on the wafer. The e-beam tool aligns each pattern file (in its final fractured form) to a mark before writing the pattern.
If your alignment tolerance is greater than ~0.5 um, then the individual chip alignment will not be necessary. Global alignment -- that is, correction for the placement and rotation of the workpiece -- can use marks which are separate and larger than those used for chip alignment. Large global alignment marks are useful for the exposure of full wafers since the machine can be programmed to search for the first mark. Typical marks used for global alignment are large crosses of width 2 to 6 um and length ~100 to 200 um, placed at the top, bottom, left, and right sides of the wafer, as illustrated in Fig. 2.27. Alternatively, a few of the marks used for chip alignment could also be used for global alignment; this would allow global alignment on small pieces of a wafer. Alignment to chip marks is especially useful as a diagnostic of the maskmaking tool, allowing the measurement of displacements as a function of chip location.
For large patterns that take a long time to write, it may improve registration and placement accuracy if the machine stops periodically (every 5 to 10 minutes is typical) to reregister to the alignment marks. This corrects for thermal or other drifts that can occur during the writing process. For single level processes or maskmaking, reregistering to a single mark is sufficient to correct for drift.
The size of a chip may be on the order of centimeters, and in photolithography the chips or entire wafers are aligned at once. While e-beam systems can align to global marks alone, the best tolerance (<0.1 m) will be achieved when the alignment marks are within several hundred micrometers of the critical region. The designer may therefore wish to split the e-beam layer into smaller sections so that critical regions can be aligned individually. If these critical regions (e.g., gates) are arranged in a regular pattern, then arranging the sequence of e-beam writing will be simple. If the critical regions are placed randomly in the chip, the designer will have a time-consuming job of arranging the e-beam sequence and avoiding field boundaries.
Alignment marks must be patterned in previous steps of the device fabrication. A "zero level" is sometimes used for the sole purpose of placing robust alignment marks on the sample before any actual device data are written. Typically the designer includes a photolithography step simply for patterning alignment marks as trenches to be etched into the substrate. The best alignment of layer 2 to layer 1 will be achieved when layer 1 contains the marks used for aligning layer 2 and when the marks are as close as possible to critical areas. If the material of layer 1 is unacceptable for alignment (e.g., a 20 nm thick metal layer) then both layers will have to be aligned to a third reference pattern (the "zero level"). Alignment to a third layer adds a factor of ~1.4 to the overlay error.
Well designed marks are commonly destroyed by processing. For example, ohmic metalizations become very rough when annealed. The rough marks are fine for optical alignment, but the lumps may cause the e-beam alignment hardware to trigger at the wrong locations. A good solution to this problem is to fabricate alignment marks as deep etched trenches (deeper than 1 m). Plasma-etched or wet-etched trenches may be used. Such pits will not change after high temperature processing (unless material is deposited in them), and (unlike Au) are compatible with MOS processing. Other examples of effective alignment marks are W on Ti, Pt on Ti, and Au on Cr. Au is compatible with GaAs processing, but to maintain a smooth film, the alignment marks must be patterned after the annealing steps. In each of these cases the Ti or Cr provides improved adhesion to the substrate. A 200 nm thick layer of Pt or Au provides a good alignment signal, and 10 to 20 nm of Ti or Cr under the high-Z material provides improved substrate adhesion. Metal films can be patterned with very smooth edges by a liftoff process using a bilayer of PMMA and P(MMA/MAA) (see Sect. 22.214.171.124). In all cases, the designer must consider the thickness, roughness, and process compatibility of the material used for e-beam alignment marks, as well as the mark shape required for specific e-beam tools.
CAD programs range from the very expensive schematic capture tools for VLSI to simple and inexpensive polygon editors. At the high end are widely used circuit capture, simulation, and layout tool sets from Cadence  and Mentor Graphics.  Other high-end packages are sold by Silvar Lisco,  Integrated Silicon Systems,  and a number of other vendors.  These tools run almost exclusively on UNIX workstations, and generate the standard intermediate format GDSII (also known as "Calma Stream" format) as well as the machine-specific MEBES format. Software tools in these sets include analog and digital simulators, silicon compilers, schematic capture, wire routers, design-rule checkers, and extensive cell libraries for CMOS, BiCMOS, and bipolar technologies.
In the mid-range of expense are the programs from Design Workshop  (DW2000) and Tanner Research  (L-Edit). Design Workshop implements a fully-functional graphical editor with the unusual feature of providing not only GDSII format, but also output in machine-specific formats for MEBES, JEOL, and Leica systems. DW2000 includes an integrated command language for algorithmic pattern definition. Design Workshop runs under the Macintosh OS, UNIX, and Windows NT. The Tanner Research tools run on PC compatibles, Macintoshes, and several UNIX workstations; output is in CIF or GDSII. Both Design Workshop and Tanner Research have implemented a less extensive set of companion tools (rule checkers, routers, simulators, etc.) and concentrate on the core graphical editors.
Inexpensive graphical editors include AutoCAD and other general-purpose CAD tools for PC compatibles and the Macintosh. AutoCAD and other similar programs generate DXF format, which must be converted to GDSII with a separate program.  AutoCAD has the disadvantage that it was not designed for lithography and so can generate patterns (such as 3D structures) that cannot be rendered by e-beam systems. Also, DXF format does not support "datatype" tags, which are used to specify individual dose values for geometrical shapes. Datatype tags are important when compensating (manually or automatically) for the proximity effect (see Sect. 2.4).
At the very low end are the free programs from UC Berkeley: Magic and OCT/VEM, which run on UNIX workstations. Magic is a widely used program geared for MOSIS-compatible CMOS processing. Magic is restricted to rectangles at right angles ("Manhattan geometry") and has no support for polygons. The VEM polygon editor in conjunction with the OCT database manager provides support for polygons. A number of companion simulation and routing tools also work with the OCT database but are distributed "as is," and without support. While these programs are distributed for only a shipping fee,  the real cost is the time and expertise required for installation and for working around bugs. Magic and VEM generate patterns in CIF format, which is supported by some mask vendors or may be translated to GDSII.
GDSII, also known as "Calma Stream", was originally developed by the Calma division of General Electric. Rights to the Calma products have changed hands several times, and are now owned by Cadence Design Systems. GDSII is by far the most stable, comprehensive, and widely used format for lithography. GDSII is a binary format that supports a hierarchical library of structures (called "cells"). Cells may contain a number of objects, including:
There are 64 available Layers, numbered 0 to 63. Each primitive object (Boundary, etc.) lies on one of these layers. Each layer number typically represents one mask or electron-beam exposure step in a process.
A specification of GDSII format appears in the appendix to this chapter, portions of which are reprinted by permission of Cadence Design Systems.
The Caltech Intermediate Format, or CIF 2.0, is specified officially in A Guide to LSI Implementation, Second Edition, by R. W. Hon and C. H. Sequin,  and a nearly identical description appears in Introduction to VLSI Systems, by C. Mead and L. Conway.  This format is far simpler than GDSII and has the advantage that it is readable, using only ASCII characters. While providing nearly all of the functionality of GDSII, there are a few differences:
CIF is widely used by universities using the Berkeley CAD tools to design circuits for the MOSIS integrated circuit foundry service.  MOSIS requires a number of sensible restrictions on CIF data: 
DXF format is produced by the program AutoCAD as well as by a number of other inexpensive CAD programs for Windows/DOS and the Macintosh. These programs were not designed for lithography and so contain structures (e.g. three-dimensional figures) that have no meaning in this area. Also, the common jargon (e.g., "cell") has been replaced with less familiar terminology (e.g. "block"). Like CIF, this format does not support datatype numbers. DXF is useful only after it has been translated into GDSII by a program such as that sold by Artwork Conversion Software  or those of various mask vendors.
In DXF there can be considerable confusion over such issues as whether an enclosed line represents a polygon or an actual line. Translation programs support different subsets of DXF and translate the structures into GDSII using various sets of rules. Users of DXF are advised to submit sample patterns for conversion before investing a lot of time in CAD work, and to bear in mind that the DXF file used for one vendor may not work at all for a different vendor. Therefore, the cost of data conversion should be considered when choosing an apparently inexpensive CAD tool.
PG3600 and its predecessor PG3000 are used primarily by optical pattern generators built by GCA. These reticle printers use a high brightness lamp and a variable rectangular shutter to print patterns onto mask plates. The rectangle can be rotated to create angled features, and rectangular "flashes" are often overlapped to create curves, circles, and other shapes. Because of its popularity in reticle generation, many e-beam systems support the use of PG3600, even though the format would normally be considered low-level and machine specific. There are a number of disadvantages over GDSII:
Conversion from one of the above formats to a machine-specific format usually involves flattening the hierarchy of cells, fracturing polygons into primitive shapes, and splitting the pattern into fields and subfields. The resulting machine-specific formats (e.g., MEBES, JEOL51, and BPD) usually use far more disk space than the hierarchical forms. These files must be carefully checked for software errors and may require manipulation for sizing, tone-reversal, mirroring, and so on. One way of verifying a conversion is simply to convert the low level format back to GDSII so that it can be displayed with the original CAD tool. Unfortunately, the pattern would have lost its cell structure, so the data set may be too large for the graphical editor. A special class of display and manipulation software is required that can handle very large, flat data sets.
The CATS program from Transcription Enterprises  and CAPROX from Sigma-C  offer not only viewing and manipulation of machine formats, but also will fracture GDSII directly into these formats. These conversion programs support machine formats from Etec Systems (MEBES, AEBLE), Hitachi, JEOL, Leica, GCA, and others. Operations include Boolean functions, tone reversal, rotation, sizing, and overlap removal. Sigma-C also offers a hierarchical proximity effect correction program. CATS can be combined with the proximity effect corrector PROXECCO from AISS GmbH. This software is an important alternative to the converters sold by e-beam manufacturers.
JEBCAD  is a less extensive, and less expensive, tool for viewing and manipulating JEOL and Leica formats. JEBCAD will read in GDSII, J01, SPD, and several low-level fractured formats; it will output machine formats for JEOL and Leica systems. Operations in JEBCAD include adding and deleting polygons, moving, copying, and adding arrays of objects.
Design Workshop  provides one of the most economical ways of producing machine specific formats for JEOL, Leica, and MEBES tools. DW2000's low-level fracturing modules are quite slow compared to alternative software, but are available at a small fraction of the cost.
Back to Top
This material is based upon work supported by the National Science Foundation under Grant No. ECCS-1542081. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
If you have a disability and are having trouble accessing information on this website or need materials in an alternate format, contact firstname.lastname@example.org for assistance.
Cornell NanoScale Science & Technology Facility (CNF)
250 Duffield Hall, Cornell University, Ithaca, New York 14853-2700
Voice: 607-255-2329, Fax: 607-255-8601, Email: email@example.com
Powered by ITX