The VB6 can establish a coordinate system based on alignment marks already on the wafer and precisely place a pattern with respect to preexisting patterns. This is possible if 1) the marks and the pattern already on the wafer have precise, well known placement; 2) the machine can find and 'locate' the alignment marks; 3) The placement of the pattern to be written with respect to the marks is known (through your CAD).
The marks used most commonly are 4 to 10 um squares made of gold, platinum or tungsten, or pits etched at least 1 um deep in the substrate. Octagonal marks and crosses may also be used but automated location of squares is easier to get working properly.
Alignment mark placement:
The alignment accuracy of the VB6 depends primarily on the preexisting relationship between pattern and alignment marks. For the pattern placement to be precise it is required that the alignment marks and the preexisting pattern have precise placement between them. This is more easily achieved if alignment marks and patterns are defined on the same lithography step on a well-calibrated machine. However, the requirements for mask geometry, material or etch depth often prevent this. The reason for these requirements is the difficulty in detecting backscattered electrons from the substrate at an incident energy of 100kV. If you cannot meet the requirements for mark detection in the pattern definition step, you must introduce an additional step to generate alignment marks that are accurately placed with respect to your pattern.
Marks and patterns generated by contact lithography in the same level can be registered by 3 or 4 marks on the whole wafer.
In the case of stepper generated marks, or marks generated by other ebeam systems there are basically two options: 1) a global alignment to locate the dies followed by die by die alignment with 3 or 4 marks; or 2) a global alignment followed by translation of the rotations/scaling/trapezium corrections to each die by registering to one mark. Other schemes can be used with more knowledge of the patterning system. If needed, known shifts can be introduced.
Alignment marks written by the VB6 yield alignment accuracies in the 10 nm range.
The preferred patterns for alignment on the VB6 are squares or octagons with 4-50 um sides.
Marks should have at least a 20 um clearance from any other structure on the sample otherwise they are not recognized.
Marks can be etched deep into the substrate (approx. 1 um for Si substrates) or preferably consist of 50-100 nm of lift-off Au metal. Other high atomic number metals such as Pt or W are also guaranteed to work. The important parameter is the difference in atomic weight between mark and substrate. The total backscatter from the mark depends on atomic weight and thickness. Aluminum is not a suitable mark material for Silicon or GaAs substrates. Note: a mark that is detected by an ebeam system at 50 KV will not necessarily be detected by our system operating at 100 KV.
Marks are exposed during registration, so usually marks can be used only once. Plan on placing additional marks for multi-level writing, and also to insure there are enough marks in case some marks are not present due to processing issues.
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The JEOL uses alignment marks to establish a coordinate system that it can use to expose patterns relative to a previously exposed pattern. The placement accuracy of these patterns depends on the accuracy of the tool used to expose the alignment marks. The most accurate alignment will always be “tool to itself”. This means that to achieve the best alignment the alignment marks should first be exposed on the JEOL. If the alignment marks are exposed with another tool, the alignment accuracy of the JEOL will be limited by the accuracy of the tool exposing the marks.
Two terms will often be used when describing alignment marks: global marks and chip marks. Global marks are typically larger marks placed at the outer edges of the wafer. These are used for course alignment and rotation adjustment. Chip marks are placed in the four corners of each chip and are used for placement, scaling, and rotation.
Global marks should be placed on the outer edges of the sample along the X and Y axis. Four global marks per sample are standard.
Chip marks should be placed at the corners of each chip. In general, a chip usually covers no more than 20mm x 20mm. Each time a chip mark is used for an alignment it is essentially rendered unusable for future alignments. If multiple levels of alignment need to be performed then multiple sets of chip marks need to be created. Each subsequent chip mark level should be offset toward the center of the chip by at least 100 microns in both the X and Y directions.
Standard global marks are crosses that are 2 millimeters long and 3 microns wide. Standard chip marks are crosses that are 60 microns long and 3 microns wide. Marks should be etched at least 1 micron into the substrate – 2 microns is ideal.
Metal liftoff can be used but it is not as reliable due to the chances of mark damage. Also, subsequent processing steps might cover the marks compromising their ability to be recognized by the alignment system. If metal liftoff is used the metal should be Au or some other dense, high atomic number metal. The thickness should be at least 50nm.
Once the CAD layout is complete and a total process flow is developed, a “zero level exposure” is done on the JEOL. This is an exposure done to only expose the alignment marks. This exposure will include the alignment marks for the JEOL and may include marks for the steppers, contact aligners, and any other tool in the process flow. This exposure is developed and etched to at least 1 micron. This exposure will ensure the maximum possible overlay accuracy for all following process steps. And etching the alignment marks (as opposed to metal liftoff) will ensure that the likelihood of damage due to chemical or thermal processing is minimized. The UNAXIS 770 Bosch etcher is a good tool for performing the alignment mark etch in Si as it has high selectivity to resist.
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