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EBL Process and Integration Library

Combining Electron Beam and Photolithography (Mix and Match)

Coming soon

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EBL on Membrane Substrates

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EBL on Insulating Substrates

During electron beam lithography, accumulation of charge from the beam on the sample must be prevented.  For metallic or semiconductive substrates, this is accomplished by grounding the substrate to the wafer holder with clips, which may have points that pierce through the resist layer to the substrate.  For masks, the chrome layer serves this purpose in addition to its function of being opaque to light during photolithography.  For insulating substrates such as quartz, a thin layer of gold is typically placed on the sample after application of the resist layer to provide a conducting layer.  Since the layer is thin, the high-energy electrons pass through the layer with little scattering.

At CNF, we use a table-top Polaron sputtering system for 120 sec to apply a layer of gold approximately 5 nm thick.  After e beam exposure and before developing the resist, the gold layer is removed by placing the sample in Transene gold etchant for 30 s and rinsing with DI water.  This process will not affect the resist or the substrate, removing the Au and allowing normal development of the resist.

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T-Gate Processes for High Electron Mobility Transistors

A trilayer resist process is typically used for forming T-gate or Mushroom gate structures.  These features are critical for realizing high quality high electron mobility transistor structures (HEMTs).

Substrate preparation: 

The substrate should be clean and dry. If necessary clean with solvents and bake. 

Resist coating process:

  • Bottom layer: PMMA.  The thickness of this layer determines the height of the gate foot.
  • Middle: Copolymer (MMA).  This should be thicker than the metal layer that will be evaporated to form the gate.
  • Top: PMMA. This layer should be thick enough to support overhang of the copolymer

Example:

  • Bottom layer: PMMA 4%, 2.4krpm, post application bake (PAB) 170 C 15 min.
  • Middle layer: Copolymer 11% (undiluted), 2.4krpm, PAB 170 C 15min.  This is good for <400 nm of metal.
  • Top layer: PMMA 4%, 2.4krpm, PAB 170 C for 15 min

 If the substrate is not conductive it should be coated with a conductive layer.  Refer to the process described in the EBL on Insulating Substrates portion of this page.

Exposure and Development:

The exposed pattern should be a path narrower than the desired gate length with an overlapping path with the width of the head. The total dose for the gate length defining center line is enough to develop away all three layers, but the dose for the head defining shape will only develop to the bottom of the Copolymer.

Example:

Exposure

  • Tool: Leica VB6
  • Exposure Conditions: 100 keV beam energy, pixel step VRU = 2, Current = 1 nA
  • Dose: 400 to 800uC/cm2 for the center line (depends on the gate foot-print) and 200-250uC/cm2 for the head
  • Pattern: The gate length should be shorter than the drawn width by 50 - 100nm

Development

  • Remove Au layer if sample was coated in Au to eliminate charging.
  • 3 steps: Toluene 0.5 - 1.5 min, Methanol:IPA (1:1)  1-2min, MIBK:IPA (1:1)  1 - 2.5 min rinsing with IPA between each development.
  • Each development should cut through a layer of resist. 

Example:

  • Toluene for 25sec followed by IPA rinse
  • Methanol:IPA (1:1) for 90sec followed by IPA rinse
  • MIBK:IPA (1:1) for 90 - 130sec depending on the gate foot-print and developing conditions. Monitoring is important. Rinse in IPA.

Descum:

General Process: O2 plasma to burn off resist residue

Example: Descum using Glen 1000 (program #3) for 45 - 60 sec

 

 

Oblique angle scanning electron microscope image of a T-gate fabricated at CNF by Yunju Sun, Project 370-89


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Nanoelectrode Fabrication

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EBL for Nanophotonics Applications

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EBL for Nanomagnetic Structures and Devices

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