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Advanced Fabrication Technology for MEMs Devices and Applications
Bulk Micromachining:
- Thru wafer technology
- Wet anisotropic etchants for silicon (100) and silicon (110)-KOH based.
- Deep reactive ion etching (DRIE): two Unaxis 770 systems with up to 6 inch capability,
etch rates up to 3 µm/min, and aspect ratios of 20-30:1.
- Polysilicon, silicon, and SOI substrates.
- Precise backside wafer alignment-EV620.
Fabrication of LPCVD and PECVD Based Films (6-inch capability):
- LPCVD Polysilicon: ultra-thin (< 100 nm) to thick 1 µm films with controlled low to stress free films.
- LPCVD N+/P+ Polysilicon (> 5e19 cm-3).
- Multilayer structures such as undoped polysilicon/low-temperature oxide (LTO)/doped polysilicon.
- LPCVD silicon nitride: stoichiometric (1100 MPa) and low stress (110-160 MPa) with thicknesses up to 2.5 µm.
- Low temperature oxide (LTO) at 425°C.
- LPCVD TEOS and oxynitride.
- PECVD: TEOS, SiO2, Si3N4, oxynitride, PSG (8at.%), BPSG, a-Si(N+/P+) with tunable stress and high conformality.
- RTA/RTP in N2/O2 to 1200°C.
- Ion implantation of B, P, As, and H to medium currents and 200 keV.
- Structural release: wet (CO2 supercritical drying), dry (SF6 and XeF2).
- Anisotropic RIE including ICP based etching of thick (10 µm) oxides and glasses.
- Aligned direct fusion bonding with high temperature annealing (1100°C)-EV501/620.
- Anodic bonding of silicon, and silicon with intermediate layers-EV501.
- In-situ thermo-compression bonding at lower temperatures ~400°C.
- Low temperature (< 400°C) bonding via plasma surface activation.
- Wafer scale packaging with hermetic sealing
- Unconventional bonding materials such as Si3N4, SiC, and GaAs.
- Use of PECVD and spin-on based intermediate films.
High Aspect Ratio MEMs:
- UV LIGA using SU8 with thicknesses up to 1 mm with aspect ratios up to 15:1 and electroplated structures.
- Hot Embossing: silicon and SU8 masters into substrates such as polycarbonate, PMMA, polystyrene, and PETG with feature sizes of 5-50 µm and aspect ratios up to 5:1 with incorporated anti-stiction layers.
- High resolution master template fabrication for molecular transfer lithography and imprint lithography.
| MEMs/Pre/Post/During-CMOS Process Integration and Development: (next) (top) |
- Thermal budget considerations for metallization, film deposition, and annealing.
- Film stress and adhesion issues.
- Film conformality and step coverage for high topology features.
- Stiction issues during release and device operation addressed with critical point drying and SAMs (OTC, FDTS, and vapor deposited).
- Process and device simulation: finite element analysis software.
- All major fabrication areas listed.
- Well characterized and controlled discrete processes.
- Process modules for integrated processing-device targeted.
- Process sequence assembly for documented run sheets.
Optical MEMs: MOEMs, optical switching, data storage, photonics.
RF MEMs: Inductors, switches (metal contact and capacitive design), actuation-electrostatic, thermal, piezoelectric (PZT and AlN), and magnetic.
Integrated MEMs: Accelerometers, pressure/chemical sensors.
Bio-MEMs: Bio-sensors, microfluidics, drug delivery systems, microarrays.
MEMS Switches for Binary Logic and Nonvolatile Memory under Hostile Environment CNF Project # 752-98 Principal Investigator: Edwin C. Kan User: Nick Y. Shen Affiliation: School of Electrical and Computer Engineering, Cornell University Contact Info: ys69@cornell.edu, kan@ece.cornell.edu
- Figure: SEM picture of a sandwich tether-shape device. The large Poly2 anchor is made to ensure that Poly1 is the only moving layer under actuation.
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CNF Project # 752-98 |
Hinged Atomic Force Microscopy Cantilevers CNF Project # 883-00 Principal Investigator: Frederick Sachs, PhD Users: Arthur Beyder, David Yang Affiliation: Physiology and Biophysics, State University of New York at Buffalo Contact Info: beyder@buffalo.edu, yxy@buffalo.edu, sachs@buffalo.edu
- Figure: [A] Dies and thin silicon membranes are fabricated by backside KOH. We use compensation structures for convex corners. [B] Membranes are patterned on topside levers. [C] Hinges are released by Bosch etch. LPCVD Si3N4 hinges are protected by SiO2 during all processing. [D] Dual-hinge & torsion levers can be fabricated using this process with modification only at the CAD level.
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CNF Project # 883-00 |
The Dynamical Properties of Micromechanical Resonators CNF Project # 891-00 Principal Investigator: Melissa A. Hines Users: Yu Wang, Joshua A. Henry Affiliation: Department of Chemistry, Cornell University Contact Info: yw55@cornell.edu, jah76@cornell.edu, Melissa.Hines@cornell.edu
- Nanomechanical resonators with Si(111) faces fabricated.
- Process uses standard Si(111) wafers (not SOI).
- Q of resonators affected by surface termination.
- Oxide-terminated resonators up to twice as lossy as H-terminated resonators.
- Figure: 7 µm wide, 250 nm thick hexagonal paddle oscillator fabricated from Si(111) wafer and suspended by 450 nm wide silicon wires.
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CNF Project # 891-00 |
Undercut Control for Surface Micromachined Oscillators CNF Project # 599-96 Principal Investigator: Harold G. Craighead Users: Rustom Bhiladvala, Rob Reichenbach Affiliation: Applied & Engineering Physics, Cornell University Contact Info: rbb32@cornell.edu, rbr9@cornell.edu, hgc1@cornell.edu
- Circular arcs (Figure 1) mark remnants of the first, long, sacrificial layer etch done before device patterning.
- Figure 1: A surface micromachined paddle, 20 µm on a side, with 2 µm beams and support undercut limited to 2 µm has been created using the technique described.
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CNF Project # 599-96 |
A Surface Micromachined 3-Axis Accelerometer CNF Project # 963-01 Principal Investigator: William N. Carr User: Lijun Jiang Affiliation: New Jersey Institute of Technology Contact Info: LJ2@njit.edu, carr@adm.njit.edu
- A three-axis accelerometer by surface micromachining.
- Fully differential capacitive readout with highly sensitive, low-noise circuit board.
- Demonstration of the feasibility for fabrication 3-axis accelerometer in surface micromachining.
- ANSYS 6.1 simulation for design improvement.
- Figure (top): SEM image of a lateral-axis accelerometer.
- Figure (bottom): Close-up view of the spring beams for lateral accelerometer.
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CNF Project # 963-01 |
Microfabricated Model Silicon Probes with Microfluidic Channels for Drug Delivery CNF Project # 319-87 Principal Investigator: Michael S. Isaacson Users: Scott Retterer, Keith Neeves Affiliation: Applied and Engineering Physics, Biomedical Engineering, Chemical Engineering, Cornell University Contact Info: str8@cornell.edu, kbn4@cornell.edu, msi4@cornell.edu
- Model silicon probes, fabricated using bulk subtractive etching techniques, have been used to stimulate a neural tissue response to chronically implanted prosthetic devices in vivo.
- Various histological techniques were used to characterize the immune response.
- Microfluidic channels to be used for local drug delivery have been incorporated into the probe design.
- Figure: Model neural probe tip with a surface micromachined fluidic channel.
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CNF Project # 319-87 |
A Microfabricated PCR-Based Biosensor CNF Project # 884-00 Principal Investigator: Dr. Carl A. Batt User: Nathaniel C. Cady Affiliation: Dept. of Microbiology, Cornell University Contact Info: ncc4@cornell.edu, cab10@cornell.edu
- An integrated DNA purification / PCR amplification device has been fabricated in a microfluidic format.
- The device is capable of purifying DNA from bacterial cells and performing PCR amplification via a miniaturized thermocycler.
- Figure: Integrated DNA purification / amplification microchip consisting of RIE-etched silicon and PECVD oxide. Inset shows the 10 µm square pillars in the purification portion of the device.
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CNF Project # 884-00 |
Photonic Bandgap Materials CNF Project # 694-98 Principal Investigator: Yuri Suzuki User: Lu Chen Affiliation: Materials Science & Engineering, Cornell University Contact Info: LC60@cornell.edu, Suzuki@ccmr.cornell.edu
- Figure: 2-D honeycomb PBC structure is etched to 8 µm deep by Cl plasma etching.
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CNF Project # 694-98 |
MEMS Device Development CNF Project # 639-97 Principal Investigator: Joel Kubby Users: Pinyen Lin, Jingkuang Chen Affiliation: Xerox Wilson Center for Research & Technology Contact Info: plin@crt.xerox.com, pgulvin@crt.xerox.com, jkubby@crt.xerox.com
- SOI-MEMS process for integrating MEMS optical switches with silicon waveguides and Arrayed Waveguide Gratings (AWG) to form Photonic Light Circuits (PLC's).
- Use of silicon platform enables integration of functions in a compact system to lower cost of components.
- Reconfigurable Optical Add/Drop Multiplexers (ROADM) and Wavelength Routers have been prototyped.
- Figure: Chip-scale Reconfigurable Optical Add/Drop Multiplexer ROADM fabricated in an SOI-MEMS technology. Use of high index contrast silicon waveguides enables the ROADM chip to have centimeter scale dimensions.
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CNF Project # 639-97 |
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